The present invention relates to electronic devices, and more particularly, but not exclusively, relates to utilization of test circuitry for debugging operations and the ability to reconfigure test circuit topology.
Testing of electronic circuit boards and corresponding component connections can be performed with a so-called “bed of nails” tester. Typically, this type of tester includes probes to contact selected electrical nodes and generate test signals to verify proper electrical continuity and isolation. With the advent of circuit boards having multiple conductive layers and more complex integrated circuit devices, bed of nails testers have often proved inadequate.
One effort to provide better testing of circuitry resulted in the Joint Test Action Group (JTAG) creation of IEEE/ANSI standard 1149.1. As used herein, “JTAG standard” refers to the latest revision of the IEEE/ANSI standard 1149.1 in effect on or before 1 Nov. 2001. The JTAG standard is based on a test bus that includes at least four signal lines: a Test Data Output (TDO) line, a Test Data Input (TDI) line, a Test Mode Select (TMS) line, and a Test Clock (TCK) line. The JTAG test bus may optionally include a fifth line for Test Logic Reset (TRST). The JTAG test bus is arranged to communicate with JTAG compliant Test Access Ports (TAPs) embedded in the circuitry to be tested. Several TAPs can be utilized in a given device under test that each have a corresponding TDO interface and TDI interface. The TDO interface of one TAP can be connected to the TDI interface of another TAP to form a serially connected chain. Test equipment can be connected to the test bus to exercise the device under test, with the TDO bus line connected to the unconnected TDI interface of the TAP at one end of the chain and the TDI bus line connected to the TDO interface of the TAP at the other end of the chain to form a serially interconnected communication ring.
In contrast, the TMS and TCK bus lines are provided to each of the TAPs in parallel. The JTAG standard defines a finite state machine synchronized by with the test clock signal TCK. The various states of this machine facilitate the communication of data or commands to the TAPs through the chain, such that a boundary scan operation can be performed. The sequence of JTAG states are provided as a function of the state of TMS relative to the number of cycles TCK has run.
With the continued increase in circuit complexity, including, but not limited to the development of “System on a Chip” (SoC) technology, it has become desirable to include many TAPs on a circuit device, and possibly in the same integrated circuit. Indeed, SoC devices typically include memory, one or more processors, and other logic that would be desirable to test. For these complex technologies, the ability to single-out circuitry associated with only one TAP or to serially concatenate less than all available TAPs can be useful in the performance of various debug operations. To conserve chip space and/or reduce or eliminate the need for debug-dedicated interconnections, there is frequently a preference to perform debug operations with existing test architecture, such as the JTAG bus and TAPs.
One attempt to utilize existing test architecture for the JTAG standard is based on the JTAG by-pass command. While this command may be used to isolate a selected TAP; it does so by hampering the restoration of instruction registers in other TAPs. In another attempt, a TAP linking module has been proposed that selectively addresses subordinate TAPs. Unfortunately, this linking module scheme requires that address information be appended to standard JTAG communication packets by the host equipment, preventing backwards compatibility. As a consequence, an additional linking module override I/O pin has been proposed. Such modifications are problematic in many instances.
Thus, there is a need for further contributions in this area of technology. The present invention addresses this need.